The present invention relates generally to digital logic circuits and more specifically to an apparatus and method for implementing a multiplexer.
Multiplexers are used extensively in many applications such as computers and telecommunications. For example, multiplexers comprise the primary portion of the register file in a field-programmable-gate-array (FPGA) implementation of a microprocessor. The problem sometimes arises, however, that the multiplexer function does not map efficiently onto four-input look-up tables, which are the basic logical building block of many FPGAs. Specifically, some FPGA synthesis tools use additional logic available in the majority of FPGAs to fit, for example, a four-to-one multiplexer into two four-input look-up tables. Unfortunately, use of this additional logic makes it unavailable for other uses and complicates the process of placement and routing. It is thus apparent that there is a need in the art for an improved multiplexer implementation.
An apparatus and associated method are provided for implementing a multiplexer. The multiplexing function is divided into two stages, the first of which outputs either a selection result or a selection signal. The selection result corresponds to one of a first set of data inputs to the first stage. The second stage selects one of a second set of data inputs to the second stage in response to the selection signal.